To enhance the integration degree of a semiconductor device, experiments for laminating a thin film transistor in three dimensions have been performed. The structure of such a semiconductor device, in which a polysilicon wiring layer including a desired impurity are also used as a conductor (electrodes) of source/drain of thin film transistor, has been reported for instance in U.S. Pat. No. 6,841,813.
However, the thin film transistor with this configuration is prone to the influence of heat processes at the time of manufacturing the semiconductor device to diffuse impurities from a polysilicon used as a source/drain region into a polysilicon of the channel layer. In addition, when the thin film transistors are laminated into multi layers, the heat processes of the lower thin film transistor and that of the upper thin film transistor are different. Therefore, there is a difference in the depth of diffusion layer (a diffusion length) between the lower thin film transistor and the upper thin film transistor. Thus, there is concern that there is a difference in characteristics between the lower thin film transistor and the upper thin film transistor.
Further, for instance in Japanese Patent Laid Open No. H11-312,809A, a structure is disclosed, in which impurity diffusion shield film is formed on the substrate and further impurities diffusing from the substrate into the crystalline semiconductor layer are shielded by forming an interface state trace film formed on the impurity diffusion shield film, and in which occurrence of the interface state at a grain boundary between the crystal semiconductor layer and the interface state trace film is inhibited.
However, the configuration in which the heat process according to thin film transistors of the lower and the upper layer is different has not been sufficiently considered. Thus, the problem, in which characteristics are different between the thin film transistors that configure a semiconductor device, has not been solved.